View ISL5420007_4128928.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL54200
Data Sheet July 11, 2007 FN6408.1
USB 2.0 High/Full Speed Multiplexer
The Intersil ISL54200 dual 2:1 multiplexer IC is a single supply part that can operate from a single 2.7V to 5.5V supply. It contains two SPDT (Single Pole/Double Throw) switches configured as a DPDT. The part was designed for switching between USB High-Speed and USB Full-Speed sources in portable battery powered products. The 7 normally-closed (NC) FSx switches can swing rail-torail and were specifically designed to pass USB full speed data signals (12Mbps) that range from 0V to 3.6V. The 4.5 normally-open (NO) HSx switches have high bandwidth and low capacitance and were specifically designed to pass USB high speed data signals (480Mbps) with minimal distortion. The part can be used in Personal Media Players and other portable battery powered devices that need to switch between a high-speed transceiver and a full-speed transceiver while connected to a single USB host (computer). The digital logic inputs are 1.8V logic compatible when operated with a 2.7V to 3.6V supply. The part has an enable pin to open all switches. It can be used to facilitate proper bus disconnect and connection when switching between the USB sources. The ISL54200 is available in a 10 Ld 3mmx3mm TDFN and a small 10 Ld 2.1mmx1.6mm TQFN packages. It operates over a temperature range of -40 to +85C.
Features
* High Speed (480Mbps) and Full Speed (12Mbps) Signaling Capability per USB 2.0 * 1.8V Logic Compatible (2.7V to +3.6V supply) * Enable Pin to Open all Switches * -3dB Frequency - HSx Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880MHz - FSx Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550MHz * Crosstalk @ 1MHz. . . . . . . . . . . . . . . . . . . . . . . . . . -70dB * Off Isolation @ 100kHz . . . . . . . . . . . . . . . . . . . . . . -98dB * Single Supply Operation (VDD) . . . . . . . . . . . . 2.7V to 5.5V * Available in Ultra-thin TQFN and TDFN Packages * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* MP3 and other Personal Media Players * Cellular/Mobile Phones * PDA's * Digital Cameras and Camcorders
Application Block Diagram
3.3V CONTROLLER VDD ISL54200 IN VBUS USB CONNECTOR LOGIC CIRCUITRY 4M DCOMD1 D+ COMD2 GND GND PORTABLE MEDIA DEVICE FSD2 FSD1 USB FULL-SPEED TRANSCEIVER HSD1 HSD2 USB HIGH-SPEED TRANSCEIVER EN
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL54200 Pinouts
ISL54200 (10 LD TDFN) TOP VIEW ISL54200 (10 LD TQFN) TOP VIEW
EN VDD IN 1 2 3 4 5 LOGIC CONTROL 10 4M 10 EN VDD 9 8 HSD1 IN COMD1 HSD2 COMD1 COMD2 GND 7 FSD1 COMD2 6 FSD2 5 GND 4 6 FSD2 3 7 FSD1 1 2 4M 9 8 HSD1 HSD2 LOGIC CONTROL
NOTE: 1. ISL54200 Switches Shown for IN = Logic "0" and EN = Logic "1".
Ordering Information
PART NUMBER (Note) ISL54200IRZ ISL54200IRZ-T ISL54200IRUZ-T PART MARKING 200Z 200Z FM TEMP. RANGE (C) -40 to +85 -40 to +85 -40 to +85 10 Ld 3x3 TDFN 10 Ld 3x3 TDFN Tape and Reel 10 Ld 2.1mmx1.6mm TQFN Tape and Reel PACKAGE (Pb-Free) PKG. DWG. # L10.3x3A L10.3x3A L10.2.1x1.6A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Truth Table
ISL54200 EN 1 1 0 IN 0 1 X FSD1, FSD2 ON OFF OFF HSD1, HSD2 OFF ON OFF
Pin Descriptions
ISL54200 PIN NO. 1 2 3 4 5 6 7 8 9 10 NAME VDD IN COMD1 COMD2 GND FSD2 FSD1 HSD2 HSD1 EN Power Supply Select Logic Control Input USB Common Port USB Common Port Ground Connection Full Speed USB Differential Port Full Speed USB Differential Port High Speed USB Differential Port High Speed USB Differential Port Bus Switch Enable FUNCTION
Logic "0" when 0.5V, Logic "1" when 1.4V with a 2.7V to 3.6V Supply. X = Don't Care
2
FN6408.1 July 11, 2007
ISL54200
Absolute Maximum Ratings
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Input Voltages FSD2, FSD1, HSD2, HSD1 (Note 2) . . . . . - 1V to ((VDD) +0.3V) IN, EN (Note 2). . . . . . . . . . . . . . . . . . . . . -0.3V to ((VDD) +0.3V) Output Voltages COMD1, COMD2 (Note 2) . . . . . . . . . . . . . . . . . . . . . . . -1V to 5V Continuous Current (HSD2, HSD1, FSD2, FSD1). . . . . . . . . 40mA Peak Current (HSD2, HSD1, FSD2, FSD1) (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 100mA ESD Rating: HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>7kV MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>400V CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.4kV
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) 10 Ld 3x3 TDFN Package . . . . . . . . . . . . . . . . . . . . 55 10 Ld TQFN Package . . . . . . . . . . . . . . . . . . . . . . 140 Maximum Junction Temperature (Plastic Package). . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range ISL54200IRZ and ISL54200IRUZ . . . . . . . . . . . . . . -40C to +85C VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 2. Signals on FSD1, FSD2, HSD1, HSD2, COMD1, COMD2, EN, IN exceeding VDD or GND by specified amount are clamped. Limit current to maximum current ratings. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V, VENH = 1.4V,
VENL = 0.5V, (Note 4), Unless Otherwise Specified. PARAMETER ANALOG SWITCH CHARACTERISTICS NC Switches (FSD1, FSD2) Analog Signal Range, VANALOG ON-Resistance, rON VDD = 3.3V, IN = 0V, EN = 3.3V VDD = 3.3V, IN = 0.5V, EN = 1.4V, ICOMx = 40mA, VFSD1 or VFSD2 = 0V to 3.3V, (See Figure 4) VDD = 3.3V, IN = 0.5V, EN = 1.4V, ICOMx = 40mA, VFSD1 or VFSD2 = Voltage at max rON over signal range of 0V to 3.3V, (Note 8) VDD = 3.3V, IN = 0.5V, EN = 1.4V, ICOMx = 40mA, VFSD1 or VFSD2 = 0V to 3.3V, (Note 7) V+ = 3.6V, IN = 3.6V, EN = 0V and 3.6V, VCOMx = 0.3V, 3V, VFSX = 3V, 0.3V V+ = 3.6V, IN = 0V, EN = 3.6V, VCOMx = 0.3V, 3V, VFSX = 0.3V, 3V Full +25 Full +25 Full +25 Full +25 Full +25 Full 0 -20 -70 -20 -70 7 0.1 4 2 2 VDD 10 15 0.35 0.4 6 8 20 70 20 70 V nA nA nA nA TEST CONDITIONS TEMP (C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS
rON Matching Between Channels, rON rON Flatness, rFLAT(ON)
OFF Leakage Current, IFSX(OFF)
ON Leakage Current, IFSX(ON)
NO Switches (HSD1, HSD2) Analog Signal Range, VANALOG ON-Resistance, rON VDD = 3.3V, IN = 3.3V, EN = 3.3V VDD = 3.3V, IN = 1.4V, EN = 1.4V, ICOMx = 1mA, VHSD2 or VHSD1 = 3.3V (See Figure 3) VDD = 3.3V, IN = 1.4V, EN = 1.4V, ICOMx = 40mA, VHSD2 or VHSD1 = 0V to 400mV (See Figure 3) VDD = 3.3V, IN = 1.4V, EN = 1.4V, ICOMx = 40mA, VHSD2 or VHSD1 = Voltage at max rON, Voltage at max rON over signal range of 0V to 400mV (Note 8) VDD = 3.3V, IN = 1.4V, EN = 1.4V, ICOMx = 40mA, VHSD2 or VHSD1 = 0V to 400mV, (Note 7) Full +25 Full +25 Full +25 Full +25 Full 0 20 4.5 0.01 0.4 VDD 30 35 6 8 0.1 0.5 1 1.5 V
ON-Resistance, rON
rON Matching Between Channels, rON rON Flatness, rFLAT(ON)
3
FN6408.1 July 11, 2007
ISL54200
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V, VENH = 1.4V,
VENL = 0.5V, (Note 4), Unless Otherwise Specified. (Continued) PARAMETER OFF Leakage Current, IHSD2(OFF) or IHSD1(OFF) TEST CONDITIONS VDD = 3.6V, IN = 0V, EN = 0 and 3.6V, VCOMD1 or VCOMD2 = 3V, 0.3V, VHSD2 or VHSD1 = 0.3V, 3V TEMP (C) +25 Full +25 Full MIN (Notes 5, 6) -20 -70 -20 -70 TYP 2 2 MAX (Notes 5, 6) UNITS 20 70 20 70 nA nA nA nA
ON Leakage Current, IHSD2(ON) or VDD = 3.6V, IN = 3.6V, EN = 3.6V, VCOMD1 or IHSD1(ON) VCOMD2 = 0.3V, 3.0V, VHSD2 or VHSD1 = 0.3V, 3.0V DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD Skew, tSKEW (HSx Switch) Total Jitter, tJ (HSx Switch) Propagation Delay, tPD (HSx Switch) Skew, tSKEW (FSx Switch) Rise/Fall Time Mismatch, tM (FSx Switch) Total Jitter, tJ (FSx Switch) Propagation Delay, tPD (FSx Switch) Crosstalk Off Isolation FSx Switch -3dB Bandwidth HSx Switch -3dB Bandwidth HSx OFF Capacitance, CHSxOFF FSx OFF Capacitance, CFSxOFF VDD = 3.3V, RL = 45, CL = 10pF, (See Figure 1) VDD = 3.3V, RL = 45, CL = 10pF, (See Figure 1) VDD = 3.3V, RL = 45, CL = 10pF, (See Figure 2) VDD = 3.3V, IN = 3.3V, EN = 3.3V, RL = 45, CL = 10pF, tR = tF = 720ps at 480Mbps, (Duty Cycle = 50%) (See Figure 7) VDD =3.3V, IN = 3.3V, EN = 3.3V, RL = 45, CL = 10pF, tR = tF = 720ps at 480Mbps VDD = 3.3V, IN = 3.3V, EN = 3.3V, RL = 45, CL = 10pF, (See Figure 7) VDD = 3.3V, IN = 0V, EN = 3.3V, RL = 39, CL = 50pF, tR = tF = 12ns at 12Mbps, (Duty Cycle = 50%) (See Figure 7) VDD = 3.3V, IN = 0V, EN = 3.3V, RL = 39, CL = 50pF, tR = tF = 12ns at 12Mbps, (Duty Cycle = 50%) VDD = 3.3V, IN = 0V, EN = 3.3V, RL = 39, CL = 50pF, tR = tF = 12ns at 12Mbps VDD = 3.3V, IN = 0V, EN = 3.3V, RL = 39, CL = 50pF, (See Figure 7) VDD = 3.3V, RL = 45, f = 1MHz (See Figure 6) VDD = 3.3V, RL = 45, f = 100kHz Signal = -10dBm, 1.0VDC offset, RL = 45, CL = 5pF Signal = -10dBm, 0.2VDC offset, RL = 45, CL = 5pF f = 1MHz, VDD = 3.3V, IN = 0V, EN = 3.3V, VHSD1 or VHSD2 = VCOMx = 0V, (See Figure 5) f = 1MHz, VDD = 3.3V, IN = 3.3V, EN = 3.3V, VFSD1 or VFSD2 = VCOMx = 0V, (See Figure 5)
+25 +25 +25 +25
-
25 15 7 50
-
ns ns ns ps
+25 +25 +25
-
210 250 0.15
-
ps ps ns
+25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25
-
10 1.6 0.9 -70 -98 550 880 6 9 12 15
-
% ns ns dB dB MHz MHz pF pF pF pF
COM ON Capacitance, CCOMX(ON) f = 1MHz, VDD = 3.3V, IN = 3.3V, EN = 3.3V, VHSD1 or VHSD2 = VCOMx = 0V, (See Figure 5) COM ON Capacitance, CCOMX(ON) f = 1MHz, VDD = 3.3V, IN = 0V, EN = 3.3V, VFSD1 or VFSD2 = VCOMx = 0V, (See Figure 5) POWER SUPPLY CHARACTERISTICS Power Supply Range, VDD Positive Supply Current, IDD VDD = 3.6V, IN = 0V or 3.6V, EN = 0V or 3.6V
Full +25 Full
2.7 -
20 -
5.5 60 80
V nA nA
4
FN6408.1 July 11, 2007
ISL54200
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V, VENH = 1.4V,
VENL = 0.5V, (Note 4), Unless Otherwise Specified. (Continued) PARAMETER DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL, VENL Input Voltage High, VINH, VENH Input Current, IINL, IENL Input Current, IINH Input Current, IENH NOTES: 4. VLOGIC = Input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Parts are 100% tested at +25C. Over temperature limits established by characterization and are not production tested. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value, between HSD2 and HSD1 or between FSD2 and FSD1. VDD = 2.7V to 3.6V VDD = 2.7V to 3.6V VDD = 3.6V, IN = 0V, EN = 0V VDD = 3.6V, IN = 3.6 VDD = 3.6V, EN = 3.6 Full Full Full Full Full 1.4 10 10 1 0.5 V V nA nA A TEST CONDITIONS TEMP (C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS
Test Circuits and Waveforms
VINH LOGIC INPUT 50% VINL tOFF SWITCH INPUT VINPUT 90% SWITCH OUTPUT 0V tON VOUT 90% VIN VINPUT SWITCH INPUT tr < 20ns tf < 20ns EN HSx or FSx COMx IN GND RL 45 CL 10pF VOUT VDD
Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray capacitance. RL ----------------------V OUT = V (INPUT) R + r L ON FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
5
FN6408.1 July 11, 2007
ISL54200 Test Circuits and Waveforms (Continued)
VDD C
VINH LOGIC INPUT VINL VINPUT
EN FSD1 or FSD2 COMx HSD1 or HSD2 IN RL 45 GND CL 10pF VOUT
SWITCH OUTPUT VOUT
90% VIN 0V tD
Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 2A. MEASUREMENT POINTS FIGURE 2. BREAK-BEFORE-MAKE TIME FIGURE 2B. TEST CIRCUIT
VDD C
VDD C
rON = V1/ICOMx
HSx
rON = V1/40mA
FSx
VHSX V1 ICOMx IN 1.4V
VFSX V1 40mA GND EN
COMx
IN
0.5V
COMx
GND
EN
1.4V
1.4V
Repeat test for all switches. FIGURE 3. HSx SWITCH rON TEST CIRCUIT
Repeat test for all switches. FIGURE 4. FSx SWITCH rON TEST CIRCUIT
6
FN6408.1 July 11, 2007
ISL54200 Test Circuits and Waveforms (Continued)
VDD C VDD C
EN
HSx or FSx
EN SIGNAL GENERATOR
HSx COMx
45
IN IMPEDANCE ANALYZER
COMx
IN VINL OR VINH VIN
GND
ANALYZER RL
COMx
FSx
GND
NC
Repeat test for all switches.
Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 5. CAPACITANCE TEST CIRCUIT
VDD tri 90% DIN+ DIN90% 50% 10% tfi tro 90% 10% OUT+ OUT90% tf0 50% tskew_o 50% 10% GND DIN143 10% 50% tskew_i DIN+ 143 15.8 COMD1 VIN 15.8 EN VIN COMD2
C
D2 CL D1 CL
OUT+ 45 OUT45
|tro-tri| Delay Due to Switch for Rising Input and Rising Output Signals. |tfo-tfi| Delay Due to Switch for Falling Input and Falling Output Signals. |tskew_0| Change in Skew through the Switch for Output Signals. |tskew_i| Change in Skew through the Switch for Input Signals. FIGURE 7B. TEST CIRCUIT FIGURE 7. SKEW TEST
FIGURE 7A. MEASUREMENT POINTS
7
FN6408.1 July 11, 2007
ISL54200 Application Block Diagram
3.3V CONTROLLER VDD ISL54200 IN VBUS USB CONNECTOR LOGIC CIRCUITRY 4M DCOMD1 D+ COMD2 GND GND PORTABLE MEDIA DEVICE FSD2 FSD1 USB FULL-SPEED TRANSCEIVER HSD1 HSD2 USB HIGH-SPEED TRANSCEIVER EN
Detailed Description
The ISL54200 device is a dual single pole/double throw (SPDT) analog switch that operates from a single DC power supply in the range of 2.7V to 5.5V. It was designed to function as a dual 2-to-1 multiplexer to select between a USB high-speed transceiver and a USB full-speed transceiver in portable battery powered products. It is offered in a TDFN package and a small TQFN package for use in MP3 players, cameras, PDAs, cellphones, and other personal media players. The device has an enable pin to open all switches. The part consists of two 7 full speed (FSx) switches and two 4.5 high speed (HSx) switches. The FSx switches can swing from 0V to VDD. They were designed to pass USB full speed (12Mbps) differential data signals with minimal distortion. The HSx switches have high bandwidth and low capacitance to pass USB high-speed (480Mbps) differential data signals with minimal edge and phase distortion. The ISL54200 was designed for MP3 players, cameras, cellphones, and other personal media player applications that have both high-speed and full-speed transceivers and need to multiplex between these USB sources to a single USB host (computer). A typical application block diagram of this functionality is shown on page 8. A detailed description of the two types of switches are provided in the following sections.
were specifically designed to pass USB full-speed (12Mbps) differential signals and meet the USB 2.0 full-speed signal quality specifications. See Figure 8. The FSx switches can also pass USB high speed signals (480Mbps) but do not quite meet the USB 2.0 high speed signal quality eye diagram compliance requirement. The maximum signal range for the FSx switches is from -1.5V to VDD. The signal voltage should not be allowed to exceed the VDD voltage rail or go below ground by more than -1.5V. When operated with a 2.7V to 3.6V supply, the FSx switches are active (turned ON) whenever the IN logic control voltage is 0.5V and the EN logic voltage 1.4V.
HSx Switches (HSD1, HSD2)
The two HSx switches (HSD2, HSD1) are bi-directional switches that can pass rail-to-rail signals. When powered with a 3.3V supply, these switches have a nominal rON of 4.5 over the signal range of 0V to 400mV with a rON flatness of 0.4. The rON matching between the HSD1 and HSD2 switches over this signal range is only 0.01, ensuring minimal impact by the switches to USB high speed signal transitions. As the signal level increases, the rON switch resistance increases. At signal level of 3.3V, the switch resistance is nominally 20. The HSx switches were specifically designed to pass USB 2.0 high-speed (480Mbps) differential signals typically in the range of 0V to 400mV. They have low capacitance and high bandwidth to pass the USB high-speed signals with minimum edge and phase distortion to meet USB 2.0 high speed signal quality specifications. See Figures 9 and 10.
FSx Switches (FSD1, FSD2)
The two FSx switches (FSD1, FSD2) are bidirectional switches that can pass rail-to-rail signals. When powered with a 3.3V supply, these switches have a nominal rON resistance of 7 over the signal range of 0V to 3.3V. They
8
FN6408.1 July 11, 2007
ISL54200
The HSx switches can also pass USB full-speed signals (12Mbps) with minimal distortion and meet all the USB requirements for USB 2.0 full-speed signaling. See Figure 11. The maximum signal range for the HSx switches is from -1.5V to VDD. The signal voltage should not be allow to exceed the VDD voltage rail or go below ground by more than -1.5V. The HSx switches are active (turned ON) whenever the IN voltage is 1.4V and the EN logic voltage 1.4V when operated with a 2.7V to 3.6V supply. media player and the computer. The device will be able to transmit and receive data from the computer at a data rate of 12Mbps. High-speed Mode If the IN pin = Logic "1" and the EN pin = Logic "1", the part will go into high-speed mode. In high-speed mode, the HSD1 and HSD2 switches are ON and the FSD1 and FSD2 switches are OFF (high impedance). When a USB cable from a computer or USB hub is connected at the common USB connector and the part is in the high-speed mode, a link will be established between the high-speed driver section of the media player and the computer. The device will be able to transmit and receive data from the computer at a data rate of 480Mbps. All Switches OFF Mode If the IN pin = Logic "0" or Logic "1" and the EN pin = Logic "0", all of the switches will turn OFF (high impedance). The all OFF state can be used to switch between the two USB sections of the media player. When disconnecting from one USB device to the other USB device, you can momentarily put the ISL54200 switch in the "all off" state in order to get the computer to disconnect from the one device so it can properly connect to the other USB device when that channel is turned ON.
ISL54200 Operation
The discussion that follows will discuss using the ISL54200 in the typical application shown in the"Application Block Diagram" on page 8. POWER The power supply connected at the VDD (pin 1) provides the DC bias voltage required by the ISL54200 part for proper operation. The ISL54200 can be operated with a VDD voltage in the range of 2.7V to 5.5V. When used in a USB application, the VDD voltage should be kept in the range of 3.0V to 5.5V to ensure you get the proper signal levels for good signal quality. A 0.01F or 0.1F decoupling capacitor should be connected from the VDD pin to ground to filter out any power supply noise from entering the part. The capacitor should be located as close to the VDD pin as possible. LOGIC CONTROL The state of the ISL54200 device is determined by the voltage at the IN pin (pin 2) and the EN pin (pin 10). IN is only active when the EN pin is logic "1" (High). Refer to the "Truth Table" on page 2. The EN pin is internally pulled low through a 4M resistor to ground. For logic "0" (Low) it can be driven low or allowed to Float. The IN pin must be driven low or high and cannot be left floating. Logic control voltage levels: EN = Logic "0" (Low) when VEN 0.5V or Floating. EN = Logic "1" (High) when VEN 1.4V IN = Logic "0" (Low) when VIN 0.5V. IN = Logic "1" (High) when VIN 1.4V Full-speed Mode If the IN pin = Logic "0" and the EN pin = Logic "1", the part will be in the full-speed mode. In this mode, the FSD1 and FSD2 switches are ON and the HSD1 and HSD2 switches are OFF (high impedance). In a typical application, VDD will be in the range of 2.8V to 3.6V and will be connected to the battery or LDO of the portable media device. When a computer or USB hub is plugged into the common USB connector and the part is in the full-speed mode, a link will be established between the full-speed driver section of the
9
FN6408.1 July 11, 2007
ISL54200 Typical Performance Curves TA = +25C, Unless Otherwise Specified
VDD = 3.3V
VOLTAGE SCALE (0.5V/DIV)
TIME SCALE (10ns/DIV)
FIGURE 8. EYE PATTERN: 12MBPS USB SIGNAL WITH FSx SWITCHES IN THE SIGNAL PATH
10
FN6408.1 July 11, 2007
ISL54200 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
VDD = 3.3V
VOLTAGE SCALE (0.1V/DIV)
TIME SCALE (0.2ns/DIV)
FIGURE 9. EYE PATTERN WITH FAR END MASK: 480MBPS USB SIGNAL WITH HSx SWITCHES IN THE SIGNAL PATH
11
FN6408.1 July 11, 2007
ISL54200 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
VDD = 3.3V
VOLTAGE SCALE (0.1V/DIV)
TIME SCALE (0.2ns/DIV)
FIGURE 10. EYE PATTERN WITH NEAR END MASK: 480MBPS USB SIGNAL WITH HSx SWITCHES IN THE SIGNAL PATH
12
FN6408.1 July 11, 2007
ISL54200 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
VDD = 3.3V
VOLTAGE SCALE (0.5V/DIV)
TIME SCALE (10ns/DIV)
FIGURE 11. EYE PATTERN: 12MBPS USB SIGNAL WITH HSx SWITCHES IN THE SIGNAL PATH
6.0 V+ = 3.3V ICOM = 40mA NORMALIZED GAIN (dB) 0.3 0.4 +85C 5.0 rON () +25C
-10 RL = 45 -20 VIN = 0.2VP-P TO 2VP-P -30 -40 -50 -60 -70 -80 -90 -110
5.5
4.5
4.0 -40C
3.5
3 0 0.1 0.2 VCOM (V) 0.001M 0.01M 0.1M 1M FREQUENCY (Hz) 10M 100M 500M
FIGURE 12. HSx SWITCH ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 13. OFF-ISOLATION
13
FN6408.1 July 11, 2007
ISL54200 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
-10 RL = 45 -20 VIN = 0.2VP-P TO 2VP-P -30 NORMALIZED GAIN (dB) -40 -50 -60 -70 -80 -90 -110 0.001M 0.01M 0.1M 1M 10M 100M 500M
FREQUENCY (Hz)
FIGURE 14. CROSSTALK
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND (TDFN Paddle Connection: Tie to GND or Float) TRANSISTOR COUNT: 98 PROCESS: Submicron CMOS
14
FN6408.1 July 11, 2007
ISL54200 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D A B
L10.2.1x1.6A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN 0.45 NOMINAL 0.50 0.127 REF 0.15 2.05 1.55 0.20 2.10 1.60 0.50 BSC 0.20 0.35 0.40 10 4 1 0 12 0.45 0.25 2.15 1.65 MAX 0.55 0.05 NOTES 5 2 3 3 4 Rev. 3 6/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. Same as JEDEC MO-255UABD except: No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm "L" MAX dimension = 0.45 not 0.42mm. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
2.50 1.75
6 INDEX AREA 2X 2X 0.10 C
N
E
1 0.10 C
2
A A1
TOP VIEW
A3 b
0.10 C 0.05 C SEATING PLANE A1 SIDE VIEW (DATUM A) PIN #1 ID 1 2 NX L N (DATUM B) N-1 e 3 (ND-1) X e BOTTOM VIEW C L NX (b) 5 SECTION "C-C" CC e (A1) NX b 5 A
C
D E e k L N
4xk
Nd Ne
0.10 M C A B 0.05 M C
L
TERMINAL TIP
FOR ODD TERMINAL/SIDE
b
0.05 MIN
L 2.00 0.80
0.275
0.10 MIN DETAIL "A" PIN 1 ID 0.50
0.25
LAND PATTERN 10
15
FN6408.1 July 11, 2007
ISL54200 Thin Dual Flat No-Lead Plastic Package (TDFN)
2X 0.10 C A A D 2X 0.10 C B
L10.3x3A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1
E
MIN 0.70 -
NOMINAL 0.75 0.20 REF
MAX 0.80 0.05
NOTES -
6 INDEX AREA TOP VIEW B
A3 b D D2 E
// A 0.10 C 0.08 C
0.20 2.95 2.25 2.95 1.45
0.25 3.0 2.30 3.0 1.50 0.50 BSC
0.30 3.05 2.35 3.05 1.55
5, 8 7, 8 7, 8 -
E2 e k
0.25 0.25
0.30 10 5
0.35
8 2 3 Rev. 3 3/06
C SEATING PLANE
SIDE VIEW
A3
L N
D2 (DATUM B) 1 2 D2/2
7
8
Nd NOTES:
6 INDEX AREA (DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
NX k E2 E2/2
2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) L1 9L 5 0.10 M C A B
7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Compliant to JEDEC MO-229-WEED-3 except for D2 dimensions.
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN6408.1 July 11, 2007

▲Up To Search▲

Price & Availability of ISL5420007

	To Download ISL5420007 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .